Design of a reversible PLD architecture

Authors:
Jae-Jin Lee;Dong-Guk Hwang;Gi-Yong Song
Affiliations:
Electronics and Telecommunications Research Institute, Korea;School of Electrical and Computer Engineering, Chungbuk National University, Cheongju, Korea;School of Electrical and Computer Engineering, Chungbuk National University, Cheongju, Korea
Venue:
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Year:
2007

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Abstract

Reversible gate is a circuit that has the same number of inputs and outputs satisfying one-to-one mapping between the vectors of input and output. So far several logic synthesis methods for reversible logic have been proposed, however, they are not able to synthesize a reversible function with input and output of arbitrary width in a constructive manner based on building blocks and interconnect. This paper proposes a new reversible PLD(programmable logic device) architecture that enables any reversible function to be implemented by cascading the building blocks, or logic units through interconnect, and fits well on arithmetic circuits in particular. Also, a new reversible gate, T2F gate, is suggested and adopted in the proposed reversible PLD architecture. Both reversible PLD and T2F gate offer significant alternative view on reversible logic synthesis.