A New Application-Specific PLD Architecture

  • Authors:

  • Jae-Jin Lee;Gi-Yong Song

  • Affiliations:

  • The authors are with the School of Electrical and Computer Engineering, Chungbuk National University, Cheongju, Korea. E-mail: ceicarus@archi.chungbuk.ac.kr, E-mail: gysong@chungbuk.ac.kr;The authors are with the School of Electrical and Computer Engineering, Chungbuk National University, Cheongju, Korea. E-mail: ceicarus@archi.chungbuk.ac.kr, E-mail: gysong@chungbuk.ac.kr

  • Venue:
  • IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  • Year:
  • 2005

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Abstract

A systolic array is an ideal for ASICs because of its massive parallelism with a minimum communication overhead, regularity and modularity. Most of commercial FPGAs cannot handle systolic structure with fast sampling rate for their general-purpose architecture nature. This paper presents a new PLD architecture targeting a super-systolic array for application-specific arithmetic operations such as MAC. This architecture combines the high performance of ASICs with the flexibility of PLDs and it offers a significant alternative view on the programmable logic devices. The super-systolic array is ideal for a newly proposed PLD architecture when it comes to area-efficiency, P&R and clock speed.