Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Generalized dominators and post-dominators
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
An OV* E algorithm for finding immediate multiple-vertex dominators
Information Processing Letters
Global Data Flow Analysis and Iterative Algorithms
Journal of the ACM (JACM)
SIAM Journal on Computing
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Finding dominators revisited: extended abstract
SODA '04 Proceedings of the fifteenth annual ACM-SIAM symposium on Discrete algorithms
A fast algorithm for finding common multiple-vertex dominators in circuit graphs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient BMC for Multi-Clock Systems with Clocked Specifications
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Assertion-Based Verification: Industry Myths to Realities (Invited Tutorial)
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
QCSP made practical by virtue of restricted quantification
IJCAI'07 Proceedings of the 20th international joint conference on Artifical intelligence
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test
IEEE Transactions on Computers
Automated design debugging with maximum satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
From RTL to silicon: the case for automated debug
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Non-solution implications using reverse domination in a modern SAT-based debugging environment
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Design debugging has become a resource-intensive bottleneck in modern VLSI CAD flows, consuming as much as 60% of the total verification effort. With typical design sizes exceeding the half-million synthesized gates mark, the growing number of blocks to be examined dramatically slows down the debugging process. The aim of this work is to prune the number of debugging iterations for finding all potential bugs, without affecting the debugging resolution. This is achieved by using structural dominance relationships between circuit components. More specifically, an iterative fixpoint algorithm is presented for finding dominance relationships between multiple-output blocks of the design. These relationships are then leveraged for the early discovery of potential bugs, along with their corrections, resulting in significant debugging speed-ups. Extensive experiments on real industrial designs show that 66% of solutions are discovered early due to dominator implications. This results in consistent performance gains in all cases and a 1.7x overall speed-up for finding all potential bugs, demonstrating the robustness and practicality of the proposed approach.