Diagnosis and correction of multiple logic design errors in digital circuits

Authors:
Pi-Yu Chung;Ibrahim N. Hajj
Affiliations:
AT&T Bell Labs, Murray Hill, NJ;Univ. of Illinois at Urbana-Champaign, Urbana
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1997

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Abstract

This paper presents a technique to correct multiple logic design errors in a gate-level netlist. A number of methods have been proposed for correcting single logic design errors. However, the extension of these methods to more than one error is still very limited. We direct our attention to circuits with a low multiplicity of errors. By assuming different error dependency scenarios, multiple errors are corrected by repeatedly applying a single error search and correction algorithm. Experimental results on correcting double-design errors and triple-design errors on ISCAS and MCNC benchmark circuits are included.