Validating the intel pentium 4 microprocessor
Proceedings of the 38th annual Design Automation Conference
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Simulation-based bug trace minimization with BMC-based refinement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On the cusp of a validation wall
IEEE Design & Test
IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
Proceedings of the 45th annual Design Automation Conference
Functional coverage measurements and results in post-Silicon validation of Core2 duo family
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Real-time lossless compression for silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
Transaction based pre-to-post silicon validation
Proceedings of the 48th Design Automation Conference
Accelerating microprocessor silicon validation by exposing ISA diversity
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Quick detection of difficult bugs for effective post-silicon validation
Proceedings of the 49th Annual Design Automation Conference
Challenges in post-silicon validation of high-speed I/O links
Proceedings of the International Conference on Computer-Aided Design
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 50th Annual Design Automation Conference
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Automatic concolic test generation with virtual prototypes for post-silicon validation
Proceedings of the International Conference on Computer-Aided Design
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The challenges of post-silicon validation are continuously increasing, driven by higher levels of integration, increased circuit complexity, and platform performance requirements. The pressure of maintaining aggressive launch schedules and containing an increased cost of validation and debug, require a holistic approach to the entire design and validation process. Post-silicon validation is very diverse, and the work starts well before first silicon is available---for example, emulation, design-for-validation (DFV) features, specialized content development, etc. This will require enhancing pre-tape out validation to have healthier first silicon, developing more standard interfaces to our validation hooks, developing more predictive tools for circuit and platform simulation and post-silicon debug, adding more formal coverage methods, and improving survivability to mitigate in-the-field issues. We view the Electronic Design Automation (EDA) industry as a key enabler to help us bridge the gaps between presilicon and post-silicon validation, and extend the considerable intellectual wealth in pre-silicon tools to the post-silicon validation area.