Automatic concolic test generation with virtual prototypes for post-silicon validation

Authors:
Kai Cong;Fei Xie;Li Lei
Affiliations:
Portland State University, Portland, OR;Portland State University, Portland, OR;Portland State University, Portland, OR
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2013

Citing 19
Cited 0

Symbolic execution and program testing

Communications of the ACM
LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation

Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Test input generation with java PathFinder

ISSTA '04 Proceedings of the 2004 ACM SIGSOFT international symposium on Software testing and analysis
DART: directed automated random testing

Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
CUTE: a concolic unit testing engine for C

Proceedings of the 10th European software engineering conference held jointly with 13th ACM SIGSOFT international symposium on Foundations of software engineering
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects

ATS '06 Proceedings of the 15th Asian Test Symposium
QEMU, a fast and portable dynamic translator

ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
Automated trace signals identification and state restoration for improving observability in post-silicon validation

Proceedings of the conference on Design, automation and test in Europe
Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA)

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Structural coverage of feasible code

Proceedings of the 5th Workshop on Automation of Software Test
Post-silicon validation challenges: how EDA and academia can help

Proceedings of the 47th Design Automation Conference
Post-silicon validation opportunities, challenges and recent advances

Proceedings of the 47th Design Automation Conference
Bridging pre-silicon verification and post-silicon validation

Proceedings of the 47th Design Automation Conference
KLEE: unassisted and automatic generation of high-coverage tests for complex systems programs

OSDI'08 Proceedings of the 8th USENIX conference on Operating systems design and implementation
Server-side verification of client behavior in online games

ACM Transactions on Information and System Security (TISSEC)
SAGE: Whitebox Fuzzing for Security Testing

Queue - Networks
Quick detection of difficult bugs for effective post-silicon validation

Proceedings of the 49th Annual Design Automation Conference
On Acceleration of SAT-Based ATPG for Industrial Designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symbolic Execution of Virtual Devices

QSIC '13 Proceedings of the 2013 13th International Conference on Quality Software

Quantified Score

Hi-index	0.00

Visualization

Abstract

Post-silicon validation is a crucial stage in the system development cycle. To accelerate post-silicon validation, high-quality tests should be ready before the first silicon prototype becomes available. In this paper, we present a concolic testing approach to generation of post-silicon tests with virtual prototypes. We identify device states under test from concrete executions of a virtual prototype based on the concept of device transaction, symbolically execute the virtual prototype from these device states to generate tests, and issue the generated tests concretely to the silicon device. We have applied this approach to virtual prototypes of three network adapters to generate their tests. The generated test cases have been issued to both virtual prototypes and silicon devices. We observed significant coverage improvement with generated test cases. Furthermore, we detected 20 inconsistencies between virtual prototypes and silicon devices, each of which reveals a virtual prototype or silicon device defect.