Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Distributed deadlock detection
ACM Transactions on Computer Systems (TOCS)
Collection and Analysis of Microprocessor Design Errors
IEEE Design & Test
Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
IODINE: a tool to automatically infer dynamic invariants for hardware designs
Proceedings of the 42nd annual Design Automation Conference
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Complementary use of runtime validation and model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
The good, the bad, and the ugly of silicon debug
Proceedings of the 43rd annual Design Automation Conference
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
On the cusp of a validation wall
IEEE Design & Test
The Daikon system for dynamic detection of likely invariants
Science of Computer Programming
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Automated Debug of Speed Path Failures Using Functional Tests
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Post-silicon validation challenges: how EDA and academia can help
Proceedings of the 47th Design Automation Conference
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
Post-silicon bug detection for variation induced electrical bugs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Transaction based pre-to-post silicon validation
Proceedings of the 48th Design Automation Conference
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
Deconfigurable microprocessor architectures for silicon debug acceleration
Proceedings of the 40th Annual International Symposium on Computer Architecture
Automatic concolic test generation with virtual prototypes for post-silicon validation
Proceedings of the International Conference on Computer-Aided Design
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We present a new technique for systematically creating postsilicon validation tests that quickly detect bugs in processor cores and uncore components (cache controllers, memory controllers, on-chip networks) of multi-core System on Chips (SoCs). Such quick detection is essential because long error detection latency, the time elapsed between the occurrence of an error due to a bug and its manifestation as an observable failure, severely limits the effectiveness of existing post-silicon validation approaches. In addition, we provide a list of realistic bug scenarios abstracted from "difficult" bugs that occurred in commercial multi-core SoCs. Our results for an OpenSPARC T2-like multi-core SoC demonstrate: 1. Error detection latencies of "typical" post-silicon validation tests can be very long, up to billions of clock cycles, especially for bugs in uncore components. 2. Our new technique shortens error detection latencies by several orders of magnitude to only a few hundred cycles for most bug scenarios. 3. Our new technique enables 2-fold increase in bug coverage. An important feature of our technique is its software-only implementation without any hardware modification. Hence, it is readily applicable to existing designs.