On automated trigger event generation in post-silicon validation
Proceedings of the conference on Design, automation and test in Europe
Defining and Providing Coverage for Assertion-Based Dynamic Verification
Journal of Electronic Testing: Theory and Applications
A cost effective approach for online error detection using invariant relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GoldMine: automatic assertion generation using data mining and static analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Detecting errors using multi-cycle invariance information
Proceedings of the Conference on Design, Automation and Test in Europe
On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
High-level synthesis of in-circuit assertions for verification, debugging, and timing analysis
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
Formally enhanced runtime verification to ensure NoC functional correctness
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Quick detection of difficult bugs for effective post-silicon validation
Proceedings of the 49th Annual Design Automation Conference
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Test compaction techniques for assertion-based test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Assertion Based Design, and more specifically, Assertion Based Verification (ABV) is quickly gaining wide acceptance in the design community. Assertions are mainly targeted at functional verification during the design and verification phases. In this paper, we concentrate on the use of assertions in post-fabrication silicon debug. We develop tools that efficiently generate the checkers from assertions, for their inclusion in the debug phase. We also detail how a checker generator can be used as a means of circuit design for certain portions of self test circuits, and more generally the design of monitoring circuits. Efficient subset partitioning of checkers for a dedicated fixed-size reprogrammable logic area is developed for efficient use of dedicated debug hardware.