Challenges in post-silicon validation of high-speed I/O links

Authors:
Chenjie Gu
Affiliations:
Intel Corp.
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2012

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Abstract

There are increasingly number of analog/mixed-signal circuits in microprocessors and SOCs. A significant portion of mixed-signal circuits are high-speed I/O links, including serial buses such as PCIE and parallel buses such as DDR. Post-silicon validation of I/O links is hard and time-consuming, and can be critical for making a product release qualification decision. In this paper, we try to summarize key challenges in post-silicon I/O validation. We discuss potential research directions and potential solutions to improve efficiency and quality of I/O validation.