Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Design for Debug: Catching Design Errors in Digital Chips
IEEE Design & Test
Facilitating Rapid First Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
The Manic Depression of Microprocessor Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
The VPC Trace-Compression Algorithms
IEEE Transactions on Computers
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Hardware Design Verification: Simulation and Formal Method-Based Approaches (Prentice Hall Modern Semiconductor Design Series)
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
Proceedings of the conference on Design, automation and test in Europe
Cell Broadband Engine Debugging for Unknown Events
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe
Post-silicon validation challenges: how EDA and academia can help
Proceedings of the 47th Design Automation Conference
Pruning-based trace signal selection algorithm
Proceedings of the 16th Asia and South Pacific Design Automation Conference
TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead
Proceedings of the 48th Design Automation Conference
Simulation-based signal selection for state restoration in silicon debug
Proceedings of the International Conference on Computer-Aided Design
Trace signal selection to enhance timing and logic visibility in post-silicon validation
Proceedings of the International Conference on Computer-Aided Design
nuTAB-BackSpace: rewriting to normalize non-determinism in post-silicon debug traces
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A hybrid approach for fast and accurate trace signal selection for post-silicon debug
Proceedings of the Conference on Design, Automation and Test in Europe
Formal-analysis-based trace computation for post-silicon debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RATS: restoration-aware trace signal selection for post-silicon validation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leveraging reconfigurability to raise productivity in FPGA functional debug
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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To locate and correct design errors that escape pre-silicon verification, silicon debug has become a necessary step in the implementation flow of digital integrated circuits. Embedded logic analysis, which employs on-chip storage units to acquire data in real time from the internal signals of the circuit-under-debug, has emerged as a powerful technique for improving observability during in-system debug. However, as the amount of data that can be acquired is limited by the on-chip storage capacity, the decision on which signals to sample is essential when it is not known a priori where the bugs will occur. In this paper, we present accelerated algorithms for restoring circuit state elements from the traces collected during a debug session, by exploiting bitwise parallelism. We also introduce new metrics that guide the automated selection of trace signals, which can enhance the real-time observability during in-system debug.