Designing UltraSparc for Testability
IEEE Design & Test
Test Features of the HP PA7100LC Processor
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testabilty Features of the MC 68060 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal-analysis-based trace computation for post-silicon debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Architecture and design of debugging logic for high-speed processor chips is somewhat of an art form, requiring the design of logic intended to isolate events that have not occurred. In fact, the goal is for such events never to occur, but history has shown that there are usually a few problems that need debugging. The Cell Broadband Engine processor is a new multicore processor that pushed the design limits. This article explores some of the debugging features that were added to the Cell Broadband Engine design to help debug unknown events.