Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
IEEE Design & Test
Clock controller design in SuperSPARC II microprocessor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Pentium® Pro Processor Design for Test and Debug
Proceedings of the IEEE International Test Conference
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip
Proceedings of the IEEE International Test Conference 2001
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
Testabilty Features of the MC 68060 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Test Features of a Core-Based Co-Processor Array for Video Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Using embedded infrastructure IP for SOC post-silicon verification
Proceedings of the 40th annual Design Automation Conference
On-chip delay measurement for silicon debug
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
A multi-core debug platform for NoC-based systems
Proceedings of the conference on Design, automation and test in Europe
Hybrid Approach to Faster Functional Verification with Full Visibility
IEEE Design & Test
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
On automated trigger event generation in post-silicon validation
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Interconnection fabric design for tracing signals in post-silicon validation
Proceedings of the 46th Annual Design Automation Conference
Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Real-time lossless compression for silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A scan cell design for scan-based debugging of an SoC with multiple clock domains
IEEE Transactions on Circuits and Systems II: Express Briefs
On-chip support for NoC-based SoC debugging
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Enabling efficient post-silicon debug by clustering of hardware-assertions
Proceedings of the Conference on Design, Automation and Test in Europe
On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
On-Chip Delay Measurement Based Response Analysis for Timing Characterization
Journal of Electronic Testing: Theory and Applications
Embedded debug architecture for bypassing blocking bugs during post-silicon validation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
For large, complex ICs, engineers need efficient techniques for debugging first silicon. The system presented here consists of an on-chip debug infrastructure and supporting debugger software,which interacts with the infrastructure to make the chip's features accessible through a serial interface.