Design for Debug: Catching Design Errors in Digital Chips
IEEE Design & Test
Test and On-line Debug Capabilities of IEEE Std 1149.1 in UltraSPARC"-III Microprocessor
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Transaction-Based Communication-Centric Debug
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Functional Debug Techniques for Embedded Systems
IEEE Design & Test
A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
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This brief presents a design-for-debug technique for a system-on-a-chip with multiple clock domains. We describe the debugging limitations that can exist between different clock domains when performing a scan-based debug methodology and then Propose a scan cell and debug control logic to address those limitations. The proposed scan cell is designed to hold and shift the current or the previous state and support online debug. The debug control logic optimizes a core test infrastructure such as the IEEE 1500 test wrapper to minimize area overhead.