Debugging Parallel Programs with Instant Replay
IEEE Transactions on Computers
ACM Computing Surveys (CSUR)
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Replay and Testing for Concurrent Programs
IEEE Software
Mtool: An Integrated System for Performance Debugging Shared Memory Multiprocessor Applications
IEEE Transactions on Parallel and Distributed Systems
microSPARCTM: A Case Study of Scan-Based Debug
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Silicon debug of a co-processor array for video applications
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Debugging of concurrent processes
PDP '95 Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing
Core-Based Scan Architecture for Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Networks on chip
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 2
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
IEEE Transactions on Computers
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Networks on chips for high-end consumer-electronics TV system architectures
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A Monitoring-Aware Network-on-Chip Design Flow
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
In-band cross-trigger event transmission for transaction-based debug
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
A formal approach to the verification of networks on chip
EURASIP Journal on Embedded Systems
Transaction-based debugging of system-on-chips with patterns
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A scan cell design for scan-based debugging of an SoC with multiple clock domains
IEEE Transactions on Circuits and Systems II: Express Briefs
On-chip support for NoC-based SoC debugging
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A high-level debug environment for communication-centric debug
Proceedings of the Conference on Design, Automation and Test in Europe
Test exploration and validation using transaction level models
Proceedings of the Conference on Design, Automation and Test in Europe
On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
| Hi-index | 0.00 |
The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC). Debugging such SOCs is hard. Based on a classification of debug scope and granularity, we propose that debugging should be communication-centric and based on transactions. Communication-centric debug focusses on the communication and the synchronisation between the IP blocks, which are implemented by the interconnect using transactions. We define and implement a modular debug architecture, based on NOC, monitors, and a dedicated high-speed event-distribution broadcast interconnect. The manufacturing-test scan chains and IEEE1149.1 test access ports (TAP) are re-used for configuration and debug data read-out. Our debug architecture requires only small changes to the functional architecture. The additional area cost is limited to the monitors and the event distribution interconnect, which are 4.5% of the NOC area, or less than 0.2% of the SOC area. The debug architecture runs at NOC functional speed and reacts very quickly to debug events to stop the SOC close in time to the condition that raised the event. The speed at which data is retrieved from the SOC after stopping using the TAP is 10 MHz. We prove our concepts and architecture with a gate-level implementation that includes the NOC, event distribution interconnect, and clock, reset, and TAP controllers. We include gate-level signal traces illustrating debug at message and transaction levels.