An integrated debugging environment for reprogrammble hardware systems
Proceedings of the sixth international symposium on Automated analysis-driven debugging
Transaction-Based Communication-Centric Debug
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
An integrated debugging environment for FPGA computing platforms
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Automated instrumentation of FPGA-based systems for system-level transaction monitoring
SOC'09 Proceedings of the 11th international conference on System-on-chip
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The fine-grained parallelism inherent in FPGAs has encouraged their use in packet processing systems. Debugging and performance evaluation of such complex designs can be significantly improved through debug information that provides a system-level perspective and hides the complexity of signal-level debugging. In this paper we present a debugging system that permits transaction-based communication-centric monitoring of packet processing systems. We demonstrate, using two different examples, how this system can improve the debugging information and abstract lower level detail. Furthermore, we demonstrate that transaction monitoring systems require fewer resources than conventional RTL debugging systems and can provide a system-level perspective not permitted by traditional tools.