Automating the Design of SOCs Using Cores
IEEE Design & Test
Logical hardware debuggers for fpga-based systems
Logical hardware debuggers for fpga-based systems
Mapping a domain specific language to a platform FPGA
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
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Modern FPGA-based systems are complex and difficult to verify. One approach to easing the verification problem and reducing perceived complexity is to use libraries of reusable functions. These reusable functions, known as intellectual property blocks, are commonly created as netlists or RTL components. Complex systems can be created from IP blocks by using highlevel design environments. These tools define the types and semantics of component interfaces which permit systems to be debugged using system-level transaction monitoring. However, the insertion of on-chip monitoring circuitry is a manual process in FPGA design flows. In this paper we present an algorithm which exploits the high-level design environment to permit automatic instrumentation of designs. We demonstrate that the algorithm can harness existing HDL generation techniques and reduce the insertion and configuration effort required of the designer.