An integrated debugging environment for reprogrammble hardware systems

Authors:
Kevin Camera;Hayden Kwok-Hay So;Robert W. Brodersen
Affiliations:
University of California, Berkeley;University of California, Berkeley;University of California, Berkeley
Venue:
Proceedings of the sixth international symposium on Automated analysis-driven debugging
Year:
2005

Citing 2
Cited 3

Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment

RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
BEE2: A High-End Reconfigurable Computing System

IEEE Design & Test

Performance analysis challenges and framework for high-performance reconfigurable computing

Parallel Computing
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Quantified Score

Hi-index	0.00

Visualization

Abstract

Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the user's design which allow the system to be monitored and updated at runtime. An assortment of logic is added before synthesis to allow variable buffering, assertion checking, and automatic breakpointing. Low-level clock control and access to off-chip storage is managed by a custom hardware operating system. Through the addition of these features, a system can be debugged directly on the hardware, bypassing simulation and reducing iterations through the design flow.