The visualization of parallel systems: an overview
Journal of Parallel and Distributed Computing - Special issue on tools and methods for visualization of parallel systems and computations
A portable debugger for parallel and distributed programs
Proceedings of the 1994 ACM/IEEE conference on Supercomputing
RISE++: A Symbolic Environment for Scan-Based Testing
IEEE Design & Test
Hardware/software co-debugging for reconfigurable computing
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Core-Based Scan Architecture for Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Debug Architecture for System on Chip Taking Full Advantage of the Test Access Port
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Transaction-Based Communication-Centric Debug
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Monitoring and debugging message passing applications with MPVisualizer
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
Transaction-based debugging of system-on-chips with patterns
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Space sensitive cache dumping for post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
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A large part of a modern SOC's debug complexity resides in the interaction between the main system components. Transaction-level debug moves the abstraction level of the debug process up from the bit and cycle level to the transactions between IP blocks. In this paper we raise the debug abstraction level further, by utilising structural and temporal abstraction techniques, combined with debug data interpretation and logical communication views. The combination of these techniques and views allow us, among others, to single-step and observe the operation of the network on a per-connection basis. As an example, we show how these higher-level abstractions have been implemented in the debug environment for the Æthereal NOC architecture and present a generic debug API, which can be used to visualise an SOC's state at the logical communication level.