Debug Architecture for System on Chip Taking Full Advantage of the Test Access Port

Authors:
E. Moerman;S. Bocq;J. Verfaillie
Affiliations:
-;-;-
Venue:
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Year:
2003

Citing 0
Cited 1

A high-level debug environment for communication-centric debug

Proceedings of the Conference on Design, Automation and Test in Europe

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Abstract

This paper describes the architecture of a structural, cost effective debug methodology, applicable for System On Chip in its system environment and targeting software as well as hardware debugging. The highly modular and flexible architecture enables an almost infinite variation of flexible configurable modules designed and hooked up to the Test Access Port (TAP). The hardware configuration flexibility is supported by software running on a PC or workstation hooked up via a POD connected to the TAP interface. The result is an easy to use implementation of increased observability.