Transaction-Based Communication-Centric Debug
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A scan cell design for scan-based debugging of an SoC with multiple clock domains
IEEE Transactions on Circuits and Systems II: Express Briefs
Effective diagnostic pattern generation strategy for transition-delay faults in full-scan SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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To debug a digital chip with a scan-based debug methodology, the chip is stopped at a certain point in time in the application. The state of the flip-flops and the memory elements is observed and compared with the simulation results. If the chip contains multiple clock domains then these clock domains must be stopped simultaneously, otherwise some of the elements in one or more of the clock domains will capture old data. The phenomenon of capturing old data is called as data invalidation. This paper describes the data invalidation problem in depthand presents a data invalidation detector circuit. An automated hierarchical data invalidation analysis tool named DIAna is also presented. By means of experimental results for two industrial SOCs, we show the amount of data invalidation that can occur during silicon debug.