Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Fault dictionary compression and equivalence class computation for sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Poirot: Applications of a Logic Fault Diagnosis Tool
IEEE Design & Test
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Reducing Test Application Time through Interleaved Scan
Proceedings of the 15th symposium on Integrated circuits and systems design
Fault Distinguishing Pattern Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Delay Defect Characteristics and Testing Strategies
IEEE Design & Test
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transition Tests for High Performance Microprocessors
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Creating small fault dictionaries [logic circuit fault diagnosis]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective software-based self-test strategies for on-line periodic testing of embedded processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Nanometric circuits and systems are increasingly susceptible to delay defects. This paper describes a strategy for the diagnosis of transition-delay faults in full-scan systems-on-a-chip (SOCs). The proposed methodology takes advantage of a suitably generated software-based self-test test set and of the scan-chains included in the final SOC design. Effectiveness and feasibility of the proposed approach were evaluated on a nanometric SOC test vehicle including an 8-bit microcontroller, some memory blocks and an arithmetic core, manufactured by STMicroelectronics. Results show that the proposed technique can achieve high diagnostic resolution while maintaining a reasonable application time.