Software-based diagnosis for processors
Proceedings of the 39th annual Design Automation Conference
Diagnostic Test Generation for Sequential Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Fault Diagnosis and Fault Model Aliasing
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Effective diagnostic pattern generation strategy for transition-delay faults in full-scan SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a procedure for generating test sequences for diagnosis of synchronous sequential circuits based on stuck at faults. In this procedure, we avoid the conventional fault-oriented test generation process by observing that a sequence to distinguish two faults can be obtained from a sequence T that detects both of the faults (such as a test sequence for fault detection) by changing T so as to “undetect” one of the faults, or change the time units or outputs where the fault is detected. To achieve this goal, the proposed procedure eliminates parts of T so as to render some of the faults undetected, or change their detection times or outputs. In the case where faults become undetected by the modified sequence, the detected faults are distinguished from the faults left undetected by the modified sequence based on pass/fall information. A pass/fall dictionary based on modified test sequences is proposed for this case. Alternatively, a standard dictionary can be used, and the proposed procedure can be used to change the time units or outputs where faults are detected in order to distinguish them. We present experimental results to demonstrate the levels of resolution that can be obtained by the proposed procedure with the proposed pass/fail dictionary, and the number of sequences required for this purpose