A fast and memory-efficient diagnostic fault simulation for sequential circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Rapid diagnostic fault simulation of stuck-at faults in sequential circuits using compact lists
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fault dictionary compression and equivalence class computation for sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
IC Failure Analysis: The Importance of Test and Diagnostics
IEEE Design & Test
Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Using Target Faults To Detect Non-Tartget Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
Diagnostic Fault Simulation of Sequential Circuits
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Probabilistic mixed-model fault diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
GARDA: a diagnostic ATPG for large synchronous sequential circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Diagnostic Test Pattern Generation for Sequential Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Diagnosis oriented test pattern generation
EURO-DAC '90 Proceedings of the conference on European design automation
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
A genetic algorithm framework for test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bridge fault diagnosis using stuck-at fault simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Software-based diagnosis for processors
Proceedings of the 39th annual Design Automation Conference
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Efficient diagnosis of faults in VLSI circuits requireshigh quality diagnostic test sets. In this work, noveltechniques for diagnostic test generation are proposedthat require significantly less time than previous methods. The set of fault pairs left undistinguished by adetection-oriented test set is first filtered to target onlytestable faults. Then diagnostic test generation is performed using a genetic algorithm (GA) combined with adiagnostic fault simulator. A new fitness metric is proposed for the GA that accurately measures the qualityof candidate sequences while requiring a limited amountof CPU time. Experimental results illustrate the effectiveness of the approach for sequential circuits.