Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Communications of the ACM
High Speed Externally Asynchronous/ Internally Clocked Systems
IEEE Transactions on Computers
Pausible clocking-based heterogeneous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Clock Synchronization through Handshake Signalling
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A NEW PARADIGM IN TEST FOR THE NEXT MILLENNIUM
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Transaction-Based Communication-Centric Debug
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
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This paper describes a novel deterministic globally-asynchronous locally-synchronous (GALS) methodology called "Synchro-Tokens.驴 Wrappers around the synchronous blocks keep the system globally asynchronous while ensuring that each transition, although arriving at a nondeterministic time, is sensed by the synchronous block during a deterministic cycle of the local clock. This determinism facilitates debug and test methodologies, such as the use of stored-pattern testers, which are effective only when the system behavior is predictable and repeatable. Applications of Synchro-Tokens to GALS systems with two or more synchronous blocks and one or more asynchronous data channels are shown. Synchro-Tokens supports both pipelined and unpipelined channels and a variety of clock generation methodologies. Novel schematic level designs of the wrapper components in a 180-nm technology are used to compare the performance of several different deterministic GALS design styles.