Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
IEEE Transactions on Computers
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Practical asynchronous interconnect network design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A flexible communication scheme for rationally-related clock frequencies
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
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STARI is a high-speed signaling technique that uses both synchronous and self-timed circuits. To demonstrate STARI, a chip has been fabricated using the MOSIS 2/spl mu/ CMOS process. In a simple test fixture, it operates at data rates of 120 Mbits/sec over a pair of wires. Because STARl uses both synchronous and self-timed circuits, it provides an opportunity to compare these two design methods. The synchronous circuits of the STARI chip achieve rates of operation two to three times those of the self-timed circuits. However, the self-timed FIFO in the receiver provides robust compensation for clock skew that could not be achieved with synchronous circuitry alone. Thus, the STARI chip demonstrates advantages of combining these two design techniques.