A scan cell design for scan-based debugging of an SoC with multiple clock domains
IEEE Transactions on Circuits and Systems II: Express Briefs
On-chip support for NoC-based SoC debugging
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Built-in functional tests for silicon validation and system integration of telecom SoC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Design for debug is the act of adding debug support to a chip's design in the realization that not every silicon chip or embedded-software application is right the first time. DFD gives debug engineers increased observability of an embedded system's internal operation. There are severe constraints, however, on the amount of debug observability that DFD can provide for error localization. In practice, to bridge the gap between the amount of on-chip data and the limited off-chip bandwidth, SoC designers use two complementary approaches to transport valuable internal debug information: run-stop debug and real-time trace debug. This article presents an overview of these techniques and describes the required hardware support. The article also shows how these techniques have been successfully applied to debug the prototype silicon and embedded software of industrial SoCs.