The Mathematical Theory of Nonblocking Switching Networks
The Mathematical Theory of Nonblocking Switching Networks
Design for Debug: Catching Design Errors in Digital Chips
IEEE Design & Test
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip
Proceedings of the IEEE International Test Conference 2001
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
A multi-core debug platform for NoC-based systems
Proceedings of the conference on Design, automation and test in Europe
Lower Bounds on Crosspoints in Concentrators
IEEE Transactions on Computers
In-System Silicon Validation and Debug
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe
Trace signal selection for visibility enhancement in post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug
Proceedings of the 49th Annual Design Automation Conference
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Post-silicon debugging of PMU integration errors using behavioral models
Integration, the VLSI Journal
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Post-silicon validation has become an essential step in the design flow of today's complex integrated circuits. One effective technique that provides real-time visibility to the circuit under debug (CUD) is to monitor and trace internal signals during its normal operation. Typically, a large number of signals are tapped and a subset of them are selected to be observed in each debug process. These trace signals need to be transferred to on-chip buffers and/or off-chip trace ports for analysis. Existing solutions use multiplexer trees or specific access networks to conduct the above duty, which, however, either provide less visibility to the CUD or result in high hardware cost. In this paper, we propose a novel trace signal interconnection fabric design to tackle the above problem. Experimental results on benchmark circuits show the efficacy of the proposed solution.