Journal of the ACM (JACM)
Real-time logics: complexity and expressiveness
Information and Computation - Special issue: selections from 1990 IEEE symposium on logic in computer science
The benefits of relaxing punctuality
Journal of the ACM (JACM)
Machine Learning
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current
ITC '04 Proceedings of the International Test Conference on International Test Conference
A mixed-signal verification kit for verification of analogue-digital circuits
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Survey of Scan Chain Diagnosis
IEEE Design & Test
Parallel Loopback Test of Mixed-Signal Circuits
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe
Automated Selection of Signals to Observe for Efficient Silicon Debug
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Interconnection fabric design for tracing signals in post-silicon validation
Proceedings of the 46th Annual Design Automation Conference
Trace signal selection for visibility enhancement in post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Chassis: A Platform for Verifying PMU Integration Using Autogenerated Behavioral Models
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Auxiliary Specifications for Context-Sensitive Monitoring of AMS Assertions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power Management Units (PMUs) are large integrated mixed-signal circuits, having several linear and switching regulators for supplying customized voltages to the components of a low power platform. The presence of analog components in the integration circuitry makes it very hard to eliminate all pre-silicon integration errors, including some common types of errors. During post-silicon debug the designer typically wants to rule out the common types of errors before considering other types of bugs. This is facilitated by a mechanism for mapping back from observed anomalies to these known types of integration errors. We present an approach that enables this task by creating a fault map through pre-silicon analysis of the PMU. The proposed pre-silicon analysis makes use of formal properties and behavioral models to accelerate simulation, and is thereby able to create the fault map within feasible limits of time. We present experimental results on industrial strength PMUs to demonstrate the feasibility of this step. We also present a post-silicon debugging approach, which uses the inverse of the fault map to shortlist the set of known types of integration errors that must be ruled out before looking for other forms of bugs.