IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosing scan clock delay faults through statistical timing pruning
Proceedings of the 48th Design Automation Conference
Proceedings of the 2012 Symposium on Theory of Modeling and Simulation - DEVS Integrative M&S Symposium
Post-silicon debugging of PMU integration errors using behavioral models
Integration, the VLSI Journal
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Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. The Achilles heel in the application of scan-based testing is the integrity of the scan chains. From 10% to 30% of all defects cause scan chains to fail, and chain failures account for almost 50% of chip failures. Therefore, scan chain failure diagnosis is important for effective scan-based testing. Chain patterns alone are sufficient to determine the fault type, but they are insufficient to pinpoint the index of a failing flip-flop. This is the fundamental motivation for chain failure diagnosis, which is the process of identifying one or multiple defective scan cells in a scan chain or defective scan-enable or clock signals. This article surveys chain fault diagnosis techniques. The authors classify these techniques into three categories: tester based, hardware based, and software based.