Discrete-event system-on-a-chip with universal event tracer and floating-point synchronizer for interoperation of a DEVS simulator and an on-chip debugger

• Authors: Daejin Park;Tag Gon Kim
• Venue: Proceedings of the 2012 Symposium on Theory of Modeling and Simulation - DEVS Integrative M&S Symposium
• Year: 2012

A newly designed discrete-event system-on-a-chip (DESoC) is proposed and implemented on a 0.18um silicon wafer using the proposed on-chip event bus architecture. The on-chip event bus of the proposed chip was designed with newly-designed hardware for the event tracer for delayed-data propagation and the floating-point synchronizer for continuous-time operation of the discrete-event system concept. This technique replaces the global bus network with the event bus and the local tracer bus, which enables a reduction of the dynamic current by preventing the propagation of the global bus transition. Using the on-chip event bus, the traditional on-chip debugger (OCD) blocks can be removed except the event-matching block, and most of the comparator logics for OCD can be moved off the target chip. We designed a USB-to-event converter dongle to replace the on-chip debugger hardware with the off-chip system and software on the host-PC side for the interoperation of the DEVS simulator and OCD. With the proposed event bus and event OCD block, the logic gates needed for the large OCD block are reduced. The DEVS simulator on a host PC is virtually connected via the USB-to-event converter dongle to the event-driven OCD implemented in the target chip. The implemented chip uses less than about 25% of the operating current used by experimental chip based on the traditional on-chip bus network. The experimental chip was implemented with 18,000 logic gates and a 4Kbyte SRAM buffer for the experimental target chip.