Exploiting hardware advances for software testing and debugging (NIER track)
Proceedings of the 33rd International Conference on Software Engineering
THeME: a system for testing by hardware monitoring events
Proceedings of the 2012 International Symposium on Software Testing and Analysis
Proceedings of the 2012 Symposium on Theory of Modeling and Simulation - DEVS Integrative M&S Symposium
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Software reliability can be improved by using code coverage analysis to ensure that all statements are executed at least once during the testing process. When full code coverage information is obtained through software code instrumentation, high runtime performance overheads are incurred. Techniques that perform deferred or selective code instrumentation have shown success in reducing run-time overheads; however, the execution profile remains distorted. Techniques have been proposed that use internal processor hardware during the data gathering process, e.g. program counter logging. These approaches have been shown to reduce overheads; but currently trade swift execution for sparse code coverage. By combining the branch-vector hardware designed for debugging modern embedded processors with on-demand code coverage analysis, we have developed a new tool which provides full code coverage, while minimizing performance distortions. Experimental results show a performance impact of only 8 - 12%, while still providing 100% code coverage information.