Rational clocking [digital systems design]

Authors:
Luis F. G. Sarmenta;Gill A. Pratt;Stephen A. Ward
Affiliations:
-;-;-
Venue:
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Year:
1995

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Abstract

Communication between independently-clocked digital subsystems typically involves a finite probability of synchronization failure whose minimization introduces delays and consequent performance costs. This paper explores a technique that eliminates both the inherent unreliability of such communication and the performance overhead it implies. Our approach maintains a known phase relationship, between clocks whose frequencies are related by a rational factor, and exploits the predictability of their relative phases to algorithmically time communications without run-time arbitration contests.