A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Diagnosis of single stuck-at faults and multiple timing faults in scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosing scan clock delay faults through statistical timing pruning
Proceedings of the 48th Design Automation Conference
An ATE assisted DFD technique for volume diagnosis of scan chains
Proceedings of the 50th Annual Design Automation Conference
Post-silicon debugging of PMU integration errors using behavioral models
Integration, the VLSI Journal
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Scan chain diagnostics have become more important than ever due to the increasing complexity of VLSI designs, as more and more scan latches/flip-flops are utilized in designs, especially in microprocessors. At the same time, the off-state leakage current of CMOS technology grows exponentially from one generation to the next one. This fact imposes a big challenge on the chip design, packaging, cooling, etc. However, innovative applications, based on the detection of Light Emission due to Off-State Leakage Current (LEOSLC) have been developed for testing and diagnosing modern VLSI circuits. In this paper, we show that LEOSLC can be used to effectively debug, diagnose, and localize defects in a broken scan chain.