IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Failure Diagnosis of Structured VLSI
IEEE Design & Test
High-Accuracy Flush-and-Scan Software Diagnostic
IEEE Design & Test
Diagnosis of Scan Chain Failures
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
An Efficient Scheme to Diagnose Scan Chains
Proceedings of the IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A technique for fault diagnosis of defects in scan chains
Proceedings of the IEEE International Test Conference 2001
Scan Chain Diagnosis Using IDDQ Current Measurement
ATS '99 Proceedings of the 8th Asian Test Symposium
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Diagnosis of scan path failures
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Diagnosis of Sequence-Dependent Chips
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Testing of Digital Systems
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current
ITC '04 Proceedings of the International Test Conference on International Test Conference
Systematic Defects in Deep Sub-Micron Technologies
ITC '04 Proceedings of the International Test Conference on International Test Conference
A statistical study of defect maps of large area VLSI IC's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Scan chain hold-time violations: can they be tolerated
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A diagnosis technique to locate single stuck-at faults and multiple timing faults in scan chains is presented. This technique applies single excitation (SE) patterns, in which only one bit is flipped in the presence of multiple faults. With SE patterns, the problem of unknown values in scan chains is eliminated. The diagnosis result is therefore deterministic, not probabilistic. In addition to the first fault, this technique also diagnoses the remaining timing faults by applying multiple excitation patterns. Experiments on benchmark circuits show that average diagnosis resolutions are mostly less than five, even for the tenth fault in the scan chain.