Diagnosis for scan-based BIST: reaching deep into the signatures
Proceedings of the conference on Design, automation and test in Europe
Diagnosis of Scan Chain Failures
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
An Efficient Scheme to Diagnose Scan Chains
Proceedings of the IEEE International Test Conference
A technique for fault diagnosis of defects in scan chains
Proceedings of the IEEE International Test Conference 2001
On Validating Data Hold Times for Flip-Flops in Sequential Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Diagnosis of scan path failures
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Diagnosis of Hold Time Defects
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains
IEEE Transactions on Computers
Quick Scan Chain Diagnosis Using Signal Profiling
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Hold time validation on silicon and the relevance of hazards in timing analysis
Proceedings of the 43rd annual Design Automation Conference
Diagnosis, modeling and tolerance of scan chain hold-time violations
Proceedings of the conference on Design, automation and test in Europe
Fault Dictionary Based Scan Chain Failure Diagnosis
ATS '07 Proceedings of the 16th Asian Test Symposium
Diagnosis of single stuck-at faults and multiple timing faults in scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosing scan clock delay faults through statistical timing pruning
Proceedings of the 48th Design Automation Conference
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Scan chain hold-time violations may occur due to manufacturing defects or to errors in timing closure process during the physical design stage. The latter type of violations prohibits the test of manufactured chips, leading to a zero yield, although these chips with scan hold-time violations may be perfectly functional. In this paper, we propose a suite of techniques which enable the diagnosis and the tolerance of scan hold-time violations. The proposed diagnosis technique can be utilized for any scan chain hold-time violation in order to pinpoint, in minimal diagnosis application time, the cause of the violation. The proposed tolerance technique is more targeted towards violations that lead to systematic failure of parts; it enables the generation of test patterns to screen out the defective parts in the presence of scan hold-time violations, perfectly restoring the yield in a cost-effective manner. The techniques that we propose are non-intrusive, as they utilize only basic scan capabilities, and thus impose no design changes. We also extend this discussion for fast-to-rise and fast-to-fall errors, intermittent scan hold-time violations, and functional hold-time violations.