A Design Diversity Metric and Analysis of Redundant Systems
IEEE Transactions on Computers
High-Accuracy Flush-and-Scan Software Diagnostic
IEEE Design & Test
Diagnosis of Scan Chain Failures
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
An Efficient Scheme to Diagnose Scan Chains
Proceedings of the IEEE International Test Conference
A technique for fault diagnosis of defects in scan chains
Proceedings of the IEEE International Test Conference 2001
Scan Chain Diagnosis Using IDDQ Current Measurement
ATS '99 Proceedings of the 8th Asian Test Symposium
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Finding a Common Fault Response for Diagnosis during Silicon Debug
Proceedings of the conference on Design, automation and test in Europe
Diagnosis of scan path failures
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Quick Scan Chain Diagnosis Using Signal Profiling
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current
ITC '04 Proceedings of the International Test Conference on International Test Conference
Using fault model relaxation to diagnose real scan chain defects
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
DERRIC: A Tool for Unified Logic Diagnosis
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Dynamic learning based scan chain diagnosis
Proceedings of the conference on Design, automation and test in Europe
Diagnosis, modeling and tolerance of scan chain hold-time violations
Proceedings of the conference on Design, automation and test in Europe
Diagnosis of single stuck-at faults and multiple timing faults in scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An algorithmic technique for diagnosis of faulty scan chains
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
The amount of die area consumed by scan chains and scan control circuit can range from 15%~30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique.