In-System Silicon Validation and Debug
IEEE Design & Test
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe
Interconnection fabric design for tracing signals in post-silicon validation
Proceedings of the 46th Annual Design Automation Conference
Post-silicon validation challenges: how EDA and academia can help
Proceedings of the 47th Design Automation Conference
On-chip support for NoC-based SoC debugging
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Interactive Debug of SoCs with Multiple Clocks
IEEE Design & Test
On Using Lossy Compression for Repeatable Experiments during Silicon Debug
IEEE Transactions on Computers
Transaction based pre-to-post silicon validation
Proceedings of the 48th Design Automation Conference
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Concurrent trace is an emerging challenge when debugging multicore systems. In concurrent trace, trace buffer becomes a bottleneck since all trace sources try to access it simultaneously. In addition, the on-chip interconnection fabric is extremely high hardware cost for the distributed trace signals. In this paper, we propose a clustering-based scheme which implements concurrent trace for debugging Network-on-Chip (NoC) based multicore systems. In the proposed scheme, a unified communication framework eliminates the requirement for interconnection fabric which is only used during debugging. With clustering scheme, multiple concurrent trace sources can access distributed trace buffer via NoC under bandwidth constraint. We evaluate the proposed scheme using Booksim and the results show the effectiveness of the proposed scheme.