Space sensitive cache dumping for post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 14.98 |
The amount of data that is observed during at-speed silicon debug is limited by the capacity of the on-chip trace buffers. To increase the debug observation window, we propose a low-cost debug architecture for at-speed silicon debug based on lossy compression. The proposed architecture enables a new debug methodology that accelerates the identification of the erroneous samples that occur intermittently over a long observation window by avoiding debug experiments that capture only error-free data. The proposed solution is applicable to both automatic test equipment-based debug and in-field debug on application boards, as long as the debug experiments are repeatable and the reference data at the probe signals are deterministically computed using a fast behavioral model of the circuit under debug.