Verification of delta-sigma converters using adaptive regression modeling
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Model Checking Based on Sequential ATPG
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
An Analysis of ATPG and SAT algorithms for Formal Verification
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Verifying Properties Using Sequential ATPG
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Verification of transient response of linear analog circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
Proceedings of the 45th annual Design Automation Conference
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Formal Verification of the Quasi-Static Behavior of Mixed-Signal Circuits by Property Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
The Case for Analog Circuit Verification
Electronic Notes in Theoretical Computer Science (ENTCS)
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
Design of mixed-signal systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to the use of scaled technologies, high levels of integration and high speeds of today's mixed-signal SoCs, the problem of validating correct operation of the SoC under electrical bugs and that of debugging yield loss due to unmodeled multi-dimensional variability effects is extremely challenging. Precise simulation of all electrical aspects of the design including the interfaces between digital and analog circuitry, coupling across power and ground planes, crosstalk, etc., across all process corners is very hard to achieve in a practical sense. The problem is expected to get worse as analog/mixed-signal/RF devices scale beyond the 45nm node and are more tightly integrated with digital systems than at present. In this context, a post-silicon validation methodology for analog/mixed-signal/RF SoCs is proposed that relies on the use of special stimulus designed to expose differences between observed DUT behavior and its predictive model. The corresponding error signature is then used to identify the likely "type" of electrical bug and its location in the design using nonlinear optimization algorithms. Results of trial experiments on RF devices are presented.