The Case for Analog Circuit Verification

Authors:
Chris J. Myers;Reid R. Harrison;David Walter;Nicholas Seegmiller;Scott Little
Affiliations:
Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, USA;Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, USA;School of Computing, University of Utah, Salt Lake City, USA;School of Computing, University of Utah, Salt Lake City, USA;School of Computing, University of Utah, Salt Lake City, USA
Venue:
Electronic Notes in Theoretical Computer Science (ENTCS)
Year:
2006

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Abstract

The traditional approach to validate analog circuits is to utilize extensive SPICE-level simulations. The main challenge of this approach is knowing when all important corner cases have been simulated. A new alternative is to utilize formal verification techniques. This paper utilizes a simple example to illustrate the potential flaws of a simulation-only based validation methodology and the potential benefits of formal verification of analog circuits.