Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

• Authors: Teresa Serrano-Gotarredona;Bernabé Linares-Barranco
• Venue: Analog Integrated Circuits and Signal Processing - Special issue on low voltage/low power design
• Year: 1999

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new five parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors Δβ/β, threshold voltages \Delta V_{T0}, bulk threshold parameters Δγ, and two components for the mobility degradation parameter mismatch \Delta \theta_{o} and \Delta \theta_{e}. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this five parameter mismatch model, an extraordinary fit between experimental and computed mismatch is obtained, including minimum length (1 μm) transistors for both ohmic and saturation regions. Standard deviations for these five parameters are obtained as well as their respective correlation coefficients, and are fitted to two dimensional surfaces f(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.