Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation
Analog Integrated Circuits and Signal Processing - Special issue on low voltage/low power design
Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits
Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Monte Carlo-Alternative Probabilistic Simulations for Analog Systems
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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Rapid decrease in feature sizes has increasingly accentuated the importance of matching between transistors. Deep sub-micron designs will further emphasize the need to focus on the effects of mismatch. Furthermore, increased efforts on high level analog device modeling will necessitate accompanying mismatch simulation and measurement methods. The deep sub-micron era forces circuit designers to learn more about the physics and the technology of transistors. This study introduces a method and assists circuit designers in including this method in their traditional design flow of circuits. By proposing a solution to the problem of building a modeling bridge between transistor mismatch and circuit response to it, we hope to enable designers to incorporate low level mismatch information in their higher level design.