Operation and modeling of the MOS transistor
Operation and modeling of the MOS transistor
Applied multivariate statistical analysis
Applied multivariate statistical analysis
Analysis and Design of Integrated Circuits
Analysis and Design of Integrated Circuits
Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation
Analog Integrated Circuits and Signal Processing - Special issue on low voltage/low power design
A Low-Power Block-Matching Cell for VideoCompression
Analog Integrated Circuits and Signal Processing
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design
Analog Integrated Circuits and Signal Processing
Symmetry constraint based on mismatch analysis for analog layout in SOI technology
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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The characterization of transistor mismatch in a standard0.7 µm CMOS technology is presented. A new methodfor matching parameter extraction has been used. Mismatch parametersbased on measurements on 10000 nMOS and 10000 pMOS transistorshave been extracted. It is observed that the threshold voltagemismatch linear dependency on the inverse of the square rootof the effective channel area no longer holds for transistorsof 0.7 µm channel length. An extended model basedon the physical causes of threshold voltage mismatch is proposed.Contrary to the established theory, it is observed that transistorswith channel length below 1 µm have less currentmismatch than what is predicted by a linear relationship withthe channel area.