Operation and modeling of the MOS transistor
Operation and modeling of the MOS transistor
Design of analog-digital VLSI circuits for telecommunications and signal processing
Analog Integrated Circuits and Signal Processing - Special issue: low-voltage low-power analog integrated circuits
Mismatch Characterization of Submicron MOS Transistors
Analog Integrated Circuits and Signal Processing
MOSFET modeling and circuit design (tutorial): re-establishing a lost connection
Proceedings of the 37th Annual Design Automation Conference
Chip design: automation comes to analog
IEEE Spectrum - IEEE medal of honor Herwig Kogelnik
An Empirical Study of Amorphous Slicing as a Program Comprehension Support Tool
IWPC '00 Proceedings of the 8th International Workshop on Program Comprehension
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets
Proceedings of the conference on Design, automation and test in Europe
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 01
2001 IEEE International Conference on Acoustics, Speech, and Signal Processing
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
SPICE models for flicker noise in n-MOSFETs from subthreshold to strong inversion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SPICE models for flicker noise in p-MOSFETs in the saturation region
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A CAD methodology for optimizing transistor current and sizing in analog CMOS design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper describes a methodology for selecting drain current, inversion level (represented by inversion coefficient), and channel length for optimum performance tradeoffs in analog CMOS design. Here, inversion coefficient replaces width as a design choice to permit a conscious optimization of inversion level while width is implicitly considered. Transconductance, gate-referred thermal-noise voltage, and drain-source saturation voltage are optimized towards weak inversion while transconductance linearity and drain-referred thermal-noise current are optimized in strong inversion. Voltage gain, flicker noise, and dc mismatch are optimized towards weak inversion at long channel length while bandwidth is optimized in strong inversion at short channel length. Optimization expressions are given along with measured transconductance efficiency and Early voltage from weak through strong inversion over a wide range of channel lengths. Transconductance efficiency and Early voltage are used as normalized measures of transconductance and drain-source resistance, independent of drain current. The methodology presented is used to design three 0.5-驴m operational transconductance amplifiers having equal 50-驴A bias currents, but different tradeoffs in gain, bandwidth, noise, and dc mismatch. The amplifiers have measured voltage gains of 16.8, 110, and 326 V/V, 驴3-dB bandwidths of 350, 51, and 5 MHz, input-referred flicker-noise voltage at 100 Hz of 2,000, 450, and 58 nV/Hz1/2, and input-referred dc mismatch voltages of 10.2, 2.2, and 1.1 mV respectively. The design methodology can be readily extended to deeper submicron CMOS processes.