Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets

Authors:
R. Schwencker;F. Schenkel;M. Pronath;H. Graeb
Affiliations:
Institute for Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany and Infineon Technologies, P.O. Box 80 09 49, 81609 Munich, Germany;Institute for Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany;Institute for Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany;Institute for Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2002

Citing 0
Cited 3

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

Analog Integrated Circuits and Signal Processing
DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing

Journal of Global Optimization
A new asynchronous parallel global optimization method based on simulated annealing and differential evolution

Applied Soft Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, a method for nominal design of analog integrated circuits is presented that includes process variations and operating ranges by worst-case parameter sets.These sets are calculated adaptively during the sizing process based on sensitivity analyses. The method leads to robust designs with high parametric yield, while being muchmore efficient than design centering methods.