Practical synthesis of high-performance analog circuits
Practical synthesis of high-performance analog circuits
Convergence of the simulated annealing algorithm for continuous global optimization
Journal of Optimization Theory and Applications
Journal of Global Optimization
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets
Proceedings of the conference on Design, automation and test in Europe
A combined heuristic optimization technique
Advances in Engineering Software - Special issue on evolutionary optimization of engineering problems
A Combined Global & Local Search (CGLS) Approach to Global Optimization
Journal of Global Optimization
A hybrid genetic algorithm and particle swarm optimization for multimodal functions
Applied Soft Computing
A distributed PSO-SVM hybrid system with feature selection and parameter optimization
Applied Soft Computing
Differential Evolution as a viable tool for satellite image registration
Applied Soft Computing
Differential evolution approach for optimal reactive power dispatch
Applied Soft Computing
Journal of Global Optimization
Evolutionary programming made faster
IEEE Transactions on Evolutionary Computation
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
IEEE Transactions on Evolutionary Computation
Circuit analysis and optimization driven by worst-case distances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Differential annealing for global optimization
ICSI'12 Proceedings of the Third international conference on Advances in Swarm Intelligence - Volume Part I
A parallel hybrid optimization algorithm for fitting interatomic potentials
Applied Soft Computing
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This paper presents a new asynchronous parallel global optimization method and its application to the automated device sizing in analog integrated circuit (IC) design. The method is based on the simulated annealing algorithm (SA), but incorporates features from differential evolution (DE) to improve the sampling efficiency and avoid the problems involved with the cooling schedule selection. A simple local search procedure is also incorporated to improve the fine tuning capabilities of the method. To reduce the optimization time, the method is designed as an asynchronous master-slave parallel system that allows simultaneous evaluation of several trial solutions. Comparison with simple SA and DE on a set of well-known analytical test functions confirms the method's efficiency. The parallel efficiency of the method is also verified by optimizing the functions with 1, 2, 4, and 8 processors. The proposed approach is also applied to several real world cases of device sizing in analog IC design. The optimization results indicate that the method is capable of finding near optimal circuits. The parallel efficiency of the method is confirmed with optimization runs on 1, 2, 4, and 8 processors.