Mismatch Characterization of Submicron MOS Transistors
Analog Integrated Circuits and Signal Processing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Placement with symmetry constraints for analog layout design using TCG-S
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symmetry within the sequence-pair representation in the context of placement for analog design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal-driven analog placement considering device matching
Proceedings of the 46th Annual Design Automation Conference
Placement optimization for yield improvement of switched-capacitor analog integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Regularity-constrained floorplanning for multi-core processors
Integration, the VLSI Journal
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The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.