Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits

Authors:
Chien-Chih Huang;Chin-Long Wey;Jwu-E Chen;Pei-Wen Luo
Affiliations:
National Central University, Taoyuan, Taiwan;National Chiao Tung University, Hsinchu, Taiwan;National Central University, Taoyuan, Taiwan;Industrial Technology Research Institute, Hsinchu, Taiwan
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
2013

Citing 9
Cited 0

Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio

Proceedings of the conference on Design, automation and test in Europe
Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Analog placement with common centroid constraints

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Symmetry constraint based on mismatch analysis for analog layout in SOI technology

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Yield evaluation of analog placement with arbitrary capacitor ratio

ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Placement optimization for yield improvement of switched-capacitor analog integrated circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits

Proceedings of the 48th Design Automation Conference
Robust Extraction of Spatial Correlation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. Placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, thus achieving higher yield performance. This study presents a new optimization criterion that quickly determines if the placement is optimal. The optimization criterion leads to the development of the concepts of C-entries and partitioned subarrays which can significantly reduce the searching space for finding the optimal/near-optimal placements on a sufficiently large array size.