Placement optimization for yield improvement of switched-capacitor analog integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 48th Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices most likely have the similar parameter variation. The key performance of many analog circuits is directly related to accurate capacitance ratios. Parallel unit capacitances have a great effect on reducing ratio mismatch. This paper addresses the impact of capacitance correlation on the yield enhancement of mixed-signal/analog integrated circuits. The relationship between correlation and variation of capacitance ratio is also presented. Therefore, both mismatch and variation of capacitance ratio can be expressed in terms of capacitance correlation. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed up the time to market.