Placement optimization for yield improvement of switched-capacitor analog integrated circuits

Authors:
Jwu-E. Chen;Pei-Wen Luo;Chin-Long Wey
Affiliations:
Department of Electrical Engineering, National Central University, Jhongli, Taoyuan, Taiwan;Department of Electrical Engineering, National Central University, Jhongli, Taoyuan, Taiwan and System-on-a- Chip Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan;Department of Electrical Engineering, National Central University, Jhongli, Taoyuan, Taiwan
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

Citing 6
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Abstract

Capacitor mismatch can generally result from two sources of error: random mismatch and systematic mismatch. Random mismatch is caused by process variation, while systematic mismatch is mainly due to an asymmetrical layout and processing gradients. A common centroid structure may be used to reduce systematic mismatch errors, but not random mismatch errors. Based on the spatial correlation model, this paper formulates the placement optimization problem of analog circuits using switched-capacitor techniques. A placement with higher correlation coefficients of the unit capacitors results in a higher acceptance rate, or chip yield. This paper proposes a heuristic algorithm that quickly and automatically derives the placement of the unit capacitors with the highest, or near-highest, correlation coefficients for yield improvement. Results show that the resultant placement derived from the proposed algorithm achieves better yield improvement than that from a common centroid approach. The proposed heuristic algorithm can be applied for any arbitrary capacitor ratios, i.e., more than two capacitors.